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| p reliminary p roduct s pecification integrated circuits group LH28F160S3HNS-TV flash memory 16mbit (2mbitx8/1mbitx16) (model number: lhf16ktv) lead-free (pb-free) spec. issue date: october 25, 2004 spec no: el16x211
lhf16ktv rev. 2.0 handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for airplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. please direct all queries regarding the products covered herein to a sales representative of the company. lhf16ktv 1 rev. 2.0 contents page 1 introduction ...................................................... 3 1.1 product overview ................................................ 3 2 principles of operation ................................ 6 2.1 data protection ................................................... 7 3 bus operation .................................................... 7 3.1 re ad ................................................................... 7 3.2 output disable .................................................... 7 3.3 standby ............................................................... 7 3.4 deep power-down .............................................. 7 3.5 read identifier codes operation ......................... 8 3.6 query operation .................................................. 8 3.7 write .................................................................... 8 4 command definitions ....................................... 8 4.1 read array command....................................... 11 4.2 read identifier codes command ...................... 11 4.3 read status register command....................... 11 4.4 clear status register command ....................... 11 4.5 query command ............................................... 12 4.5.1 block status register .................................. 12 4.5.2 cfi query identification string..................... 13 4.5.3 system interface information....................... 13 4.5.4 device geometry definition ......................... 14 4.5.5 scs oem specific extended query table .. 14 4.6 block erase command...................................... 15 4.7 full chip erase command ................................ 15 4.8 word/byte write command............................... 16 4.9 multi word/byte write command ...................... 16 4.10 block erase suspend command..................... 17 4.11 (multi) word/byte write suspend command... 17 4.12 set block lock-bit command.......................... 18 4.13 clear block lock-bits command..................... 18 4.14 sts configuration command ......................... 19 page 5 design considerations .................................30 5.1 three-line output control .................................30 5.2 sts and block erase, full chip erase, (multi) word/byte write and block lock-bit configuration polling................................................................ 30 5.3 power supply decoupling ..................................30 5.4 v pp trace on printed circuit boards ..................30 5.5 v cc , v pp , rp# transitions .................................31 5.6 power-up/down protection ................................31 5.7 power dissipation ..............................................31 6 electrical specifications ...........................32 6.1 absolute maximum ratings ............................... 32 6.2 operating conditions .........................................32 6.2.1 capacitance .................................................32 6.2.2 ac input/output test conditions.................. 33 6.2.3 dc characteristics ........................................34 6.2.4 ac characteristics - read-only operations .36 6.2.5 ac characteristics - write operations ..........39 6.2.6 alternative ce#-controlled writes ................42 6.2.7 reset operations .........................................45 6.2.8 block erase, full chip erase, (multi) word/byte write and block lock-bit configuration performance ...........................46 7 additional information ................................48 7.1 ordering information ..........................................48 8 package and packing specification ........49 lhf16ktv 2 rev. 2.0 LH28F160S3HNS-TV 16m-bit (2mbx8/1mbx16) smart 3 flash memory smart 3 technology 2.7v or 3.3v v cc 2.7v, 3.3v or 5v v pp common flash interface (cfi) universal & upgradable interface scalable command set (scs) high speed write performance 32 bytes x 2 plane page buffer 2.7 s/byte write transfer rate high speed read performance 100ns(3.3v0.3v), 120ns(2.7v-3.6v) operating temperature -40c to +85c enhanced automated suspend options write suspend to read block erase suspend to write block erase suspend to read high-density symmetrically-blocked architecture thirty-two 64k-byte erasable blocks sram-compatible write interface user-configurable x8 or x16 operation enhanced data protection features absolute protection with v pp =gnd flexible block locking erase/write lockout during power transitions extended cycling capability 100,000 block erase cycles 3.2 million block erase cycles/chip low power management deep power-down mode automatic power savings mode decreases i cc in static mode automated write and erase command user interface status register industry-standard packaging 56-lead ssop etox tm* v nonvolatile flash technology cmos process (p-type silicon substrate) not designed or rated as radiation hardened sharp?s LH28F160S3HNS-TV flash memory with smart 3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, simms and memory cards. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F160S3HNS-TV offers three levels of protection: absolute protection with v pp at gnd, selective hardware block locking, or flexible software block locking. these alternatives give designers ultimate control of their code security needs. the LH28F160S3HNS-TV is conformed to the flash scalable command set (scs) and the common flash interface (cfi) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. the LH28F160S3HNS-TV is manufactured on sharp?s 0.35m etox tm * v process technology. it come in industry-standard package: the 56-lead ssop ideal for board constrained applications. *etox is a trademark of intel corporation. lhf16ktv 3 rev. 2.0 1 introduction this datasheet contains LH28F160S3HNS-TV specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications. 1.1 product overview the LH28F160S3HNS-TV is a high-performance 16m-bit smart 3 flash memory organized as 2mbx8/1mbx16. the 2mb of data is arranged in thirty-two 64k-byte blocks which are individually erasable, lockable, and unlockable in-system. the memory map is shown in figure 3. smart 3 technology provides a choice of v cc and v pp combinations, as shown in table 1, to meet system performance and power expectations. 2.7v v cc consumes approximately one-fifth the power of 5v v cc . v pp at 2.7v, 3.3v and 5v eliminates the need for a separate 12v converter, while v pp =5v maximizes erase and write performance. in addition to flexible erase and program voltages, the dedicated v pp pin gives complete data protection when v pp v pplk . table 1. v cc and v pp voltage combinations offered by smart 3 technology v cc voltage v pp voltage 2.7v 2.7v, 3.3v, 5v 3.3v 3.3v, 5v internal v cc and v pp detection circuitry automatically configures the device for optimized read and write operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. a block erase operation erases one of the device?s 64k-byte blocks typically within 0.41s (3.3v v cc , 5v v pp ) independent of other blocks. each block can be independently erased 100,000 times (3.2 million block erases per device). block erase suspend mode allows system software to suspend block erase to read or write data from any other block. a word/byte write is performed in byte increments typically within 12.95s (3.3v v cc , 5v v pp ). a multi word/byte write has high speed write performance of 2.7s/byte (3.3v v cc , 5v v pp ). (multi) word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. individual block locking uses a combination of bits and wp#, thirty-two block lock-bits, to lock and unlock blocks. block lock-bits gate block erase, full chip erase and (multi) word/byte write operations. block lock-bit configuration operations (set block lock-bit and clear block lock-bits commands) set and cleared block lock-bits. the status register indicates when the wsm?s block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished. the sts output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using sts minimizes both cpu overhead and system power consumption. sts pin can be configured to different states using the configuration command. the sts pin defaults to ry/by# operation. when low, sts indicates that the wsm is performing a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. sts-high z indicates that the wsm is ready for a new command, block erase is suspended and (multi) word/byte write are inactive, (multi) word/byte write are suspended, or the device is in deep power-down mode. the other 3 alternate configurations are all pulse mode for use as a system interrupt. the access time is 100ns (t avqv ) over the extended temperature range (-40c to +85c) and v cc supply voltage range of 3.0v-3.6v. at lower v cc voltage, the access time is 120ns (2.7v-3.6v). the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i ccr current is 3 ma at 3.3v v cc . when either ce 0 # or ce 1 #, and rp# pins are at v cc , the i cc cmos standby mode is enabled. when the rp# pin is at gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phel ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. the device is available in 56-lead ssop (shrink small outline package). pinout is shown in figure 2. output input buffer buffer output multiplexer i/o logic command register v cc ce# we# rp# oe# idenrifier register status register data comparator y gating y decoder decoder x 32 64kbyte blocks input buffer address latch address counter write state machine program/erase voltage switch sts v pp v cc gnd a 0 -a 20 dq 0 -dq 15 query rom register data buffer page wp# byte# multiplexer 56 lead ssop pinout 1.8mm x 16mm x 23.7mm top view 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 18 21 22 23 24 25 26 27 28 41 42 43 44 45 46 47 48 29 30 31 32 33 34 35 36 37 38 39 40 49 50 51 52 53 54 55 56 we# oe# sts dq 7 dq 6 dq 5 dq 4 v cc wp# dq 15 dq 14 dq 13 dq 12 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 ce 0 # v cc nc gnd a 20 nc ce 1 # gnd gnd dq 3 dq 2 dq 1 dq 0 a 0 nc nc byte# v cc dq 11 dq 10 dq 9 dq 8 v pp rp# a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 1 a 2 a 3 lhf16ktv 4 rev. 2.0 figure 1. block diagram figure 2. ssop 56-lead pinout lhf16ktv 5 rev. 2.0 table 2. pin descriptions symbol type name and function a 0 -a 20 input address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. a 0 : byte select address. not used in x16 mode(can be floated). a 1 -a 4 : column address. selects 1 of 16 bit lines. a 5 -a 15 : row address. selects 1 of 2048 word lines. a 16 -a 20 : block address. dq 0 -dq 15 input/ output data input/outputs: dq 0 -dq 7 :inputs data and commands during cui write cycles; outputs data during memory array, status register, query, and identifier code read cycles. data pins float to high- impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. dq 8 -dq 15 :inputs data during cui write cycles in x16 mode; outputs data during memory array read cycles in x16 mode; not used for status register, query and identifier code read mode. data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode(byte#=v il ). data is internally latched during a write cycle. ce 0 #, ce 1 # input chip enable: activates the device?s control logic, input buffers decoders, and sense amplifiers. either ce 0 # or ce 1 # v ih deselects the device and reduces power consumption to standby levels. both ce 0 # and ce 1 # must be v il to select the devices. rp# input reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp# v ih enables normal operation. when driven v il , rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. oe# input output enable: gates the device?s outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. sts open drain output sts (ry/by#): indicates the status of the internal wsm. when configured in level mode (default mode), it acts as a ry/by# pin. when low, the wsm is performing an internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit configuration). sts high z indicates that the wsm is ready for new commands, block erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or the device is in deep power-down mode. for alternate configurations of the status pin, see the configuration command. wp# input write protect: master control for block locking. when v il , locked blocks can not be erased and programmed, and block lock-bits can not be set and reset. byte# input byte enable: byte# v il places device in x8 mode. all data is then input or output on dq 0-7 , and dq 8-15 float. byte# v ih places the device in x16 mode , and turns off the a 0 input buffer. v pp supply block erase, full chip erase, (multi) word/byte write, block lock- bit configuration power supply: for erasing array blocks, writing bytes or configuring block lock-bits. with v pp v pplk , memory contents cannot be altered. block erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid v pp (see dc characteristics) produce spurious results and should not be attempted. v cc supply device power supply: internal detection configures the device for 2.7v or 3.3v operation. to switch from one voltage to another, ramp v cc down to gnd and then ramp v cc to the new voltage. do not float any power pins. with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see dc characteristics) produce spurious results and should not be attempted. gnd supply ground: do not float any ground pins. nc no connect: lead is not internal connected; it may be driven or floated. 1fffff 1f0000 1effff 1e0000 1dffff 1d0000 1cffff 1c0000 1bffff 1b0000 1affff 1a0000 19ffff 190000 18ffff 180000 17ffff 170000 16ffff 160000 15ffff 150000 14ffff 140000 13ffff 130000 12ffff 120000 11ffff 110000 10ffff 100000 0fffff 0f0000 0effff 0e0000 0dffff 0d0000 0cffff 0c0000 0bffff 0b0000 0affff 0a0000 09ffff 090000 08ffff 080000 07ffff 070000 06ffff 060000 05ffff 050000 04ffff 040000 03ffff 030000 02ffff 020000 01ffff 010000 00ffff 000000 64k-byte block 27 64k-byte block 28 64k-byte block 26 64k-byte block 25 64k-byte block 24 64k-byte block 21 64k-byte block 29 64k-byte block 30 64k-byte block 31 64k-byte block 20 64k-byte block 19 64k-byte block 18 64k-byte block 17 64k-byte block 16 64k-byte block 23 64k-byte block 22 64k-byte block 11 64k-byte block 12 64k-byte block 10 64k-byte block 9 64k-byte block 8 64k-byte block 5 64k-byte block 13 64k-byte block 14 64k-byte block 15 64k-byte block 4 64k-byte block 3 64k-byte block 2 64k-byte block 1 64k-byte block 0 64k-byte block 7 64k-byte block 6 lhf16ktv 6 rev. 2.0 2 principles of operation the LH28F160S3HNS-TV flash memory includes an on-chip wsm to manage block erase, full chip erase, (multi) word/byte write and block lock-bit configuration functions. it allows for: 100% ttl-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations. status register, query structure and identifier codes can be accessed through the cui independent of the v pp voltage. high voltage on v pp enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. all functions associated with altering memory contents ? block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, status, query and identifier codes ? are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the block erase, full chip erase, (multi) word/byte write and block lock- bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latch during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, outputs query structure or outputs status register data. interface software that initiates and polls progress of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read or write data from any other block. write suspend allows system software to suspend a (multi) word/byte write to read data from any other flash memory array location. figure 3. memory map lhf16ktv 7 rev. 2.0 2.1 data protection depending on the application, the system designer may choose to make the v pp power supply switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to v pph1/2/3 . the device accommodates either design practice and encourages optimization of the processor-memory interface. when v pp v pplk , memory contents cannot be altered. the cui, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to v pp . all write functions are disabled when v cc is below the write lockout voltage v lko or when rp# is at v il . the device?s block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations. 3 bus operation the local cpu reads and writes flash memory in- system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes, query structure, or status register independent of the v pp voltage. rp# must be at v ih . the first task is to write the appropriate read mode command (read array, read identifier codes, query or read status register) to the cui. upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. five control pins dictate the data flow in and out of the component: ce# (ce 0 #, ce 1 #), oe#, we#, rp# and wp#. ce 0 #, ce 1 # and oe# must be driven active to obtain data at the outputs. ce 0 #, ce 1 # is the device selection control, and when active enables the selected memory device. oe# is the data output (dq 0 -dq 15 ) control and when active drives the selected memory data onto the i/o bus. we# and rp# must be at v ih . figure 17, 18 illustrates a read cycle. 3.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 -dq 15 are placed in a high-impedance state. 3.3 standby either ce 0 # or ce 1 # at a logic-high level (v ih ) places the device in standby mode which substantially reduces device power consumption. dq 0 -dq 15 outputs are placed in a high-impedance state independent of oe#. if deselected during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 deep power-down rp# at v il initiates the deep power-down mode. in read modes, rp#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. rp# must be held low for a minimum of 100 ns. time t phqv is required after return from power-down until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration modes, rp#-low will abort the operation. sts remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. 00ffff 000006 000004 000002 000000 01ffff 010006 010004 010003 010000 1fffff 1f0006 1f0004 1f0003 1f0000 reserved for future implementation block 31 status code block 31 (blocks 2 through 30) device code manufacturer code reserved for future implementation block 1 reserved for future implementation block 0 reserved for future implementation block 1 status code block 0 status code reserved for future implementation 1effff 020000 1f0005 010005 000005 000003 000001 lhf16ktv 8 rev. 2.0 3.5 read identifier codes operation the read identifier codes operation outputs the manufacturer code, device code, block status codes for each block (see figure 4). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block status codes identify locked or unlocked block setting and erase completed or erase uncompleted condition. figure 4. device identifier code memory map 3.6 query operation the query operation outputs the query structure. query database is stored in the 48byte rom. query structure allows system software to gain critical information for controlling the flash component. query structure are always presented on the lowest- order data output (dq 0 -dq 7 ) only. 3.7 write writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when v cc =v cc1/2 and v pp =v pph1/2/3 , the cui additionally controls block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the word/byte write command requires the command and address of the location to be written. set block lock-bit command requires the command and block address within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figures 19 and 20 illustrate we# and ce#-controlled write operations. 4 command definitions when the v pp voltage v pplk, read operations from the status register, identifier codes, query, or blocks are enabled. placing v pph1/2/3 on v pp enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands. lhf16ktv 9 rev. 2.0 table 3. bus operations(byte#=v ih ) mode notes rp# ce 0 # ce 1 # oe# we# address v pp dq 0-15 sts read 1,2,3,9 v ih v il v il v il v ih x x d out x output disable 3 v ih v il v il v ih v ih x x high z x standby 3 v ih v ih v ih v il v ih v il v ih x x x x high z x deep power-down 4 v il x x x x x x high z high z read identifier codes 9 v ih v il v il v il v ih see figure 4 x note 5 high z query 9 v ih v il v il v il v ih see table 7~11 x note 6 high z write 3,7,8,9 v ih v il v il v ih v il x x d in x table 3.1. bus operations(byte#=v il ) mode notes rp# ce 0 # ce 1 # oe# we# address v pp dq 0-7 sts read 1,2,3,9 v ih v il v il v il v ih x x d out x output disable 3 v ih v il v il v ih v ih x x high z x standby 3 v ih v ih v ih v il v ih v il v ih x x x x high z x deep power-down 4 v il x x x x x x high z high z read identifier codes 9 v ih v il v il v il v ih see figure 4 x note 5 high z query 9 v ih v il v il v il v ih see table 7~11 x note 6 high z write 3,7,8,9 v ih v il v il v ih v il x x d in x notes: 1. refer to dc characteristics. when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2/3 for v pp . see dc characteristics for v pplk and v pph1/2/3 voltages. 3. sts is v ol (if configured to ry/by# mode) when the wsm is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. it is floated during when the wsm is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or deep power-down mode. 4. rp# at gnd 0.2v ensures the lowest deep power-down current. 5. see section 4.2 for read identifier code data. 6. see section 4.5 for query data. 7. command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when v pp =v pph1/2/3 and v cc =v cc1/2 . 8. refer to table 4 for valid d in during a write operation. 9. don?t use the timing both oe# and we# are v il . lhf16ktv 10 rev. 2.0 table 4. command definitions (10) bus cycles notes first bus cycle second bus cycle command req?d oper (1) addr (2) data (3) oper (1) addr (2) data (3) read array/reset 1 write x ffh read identifier codes 2 4 write x 90h read ia id query 2 write x 98h read qa qd read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase setup/confirm 2 5 write ba 20h write ba d0h full chip erase setup/confirm 2 write x 30h write x d0h word/byte write setup/write 2 5,6 write wa 40h write wa wd alternate word/byte write setup/write 2 5,6 write wa 10h write wa wd multi word/byte write setup/confirm 4 9 write wa e8h write wa n-1 block erase and (multi) word/byte write suspend 1 5 write x b0h confirm and block erase and (multi) word/byte write resume 1 5 write x d0h block lock-bit set setup/confirm 2 7 write ba 60h write ba 01h block lock-bit reset setup/confirm 2 8 write x 60h write x d0h sts configuration level-mode for erase and write (ry/by# mode) 2 write x b8h write x 00h sts configuration pulse-mode for erase 2 write x b8h write x 01h sts configuration pulse-mode for write 2 write x b8h write x 02h sts configuration pulse-mode for erase and write 2 write x b8h write x 03h notes: 1. bus operations are defined in table 3 and table 3.1. 2. x=any valid address within the device. ia=identifier code address: see figure 4. qa=query offset address. ba=address within the block being erased or locked. wa=address of memory location to be written. 3. srd=data read from status register. see table 14 for a description of the status register bits. wd=data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id=data read from identifier codes. qd=data read from query database. 4. following the read identifier codes command, read operations access manufacturer, device and block status codes. see section 4.2 for read identifier code data. 5. if the block is locked, wp# must be at v ih to enable block erase or (multi) word/byte write operations. attempts to issue a block erase or (multi) word/byte write to a locked block while rp# is v ih . 6. either 40h or 10h are recognized by the wsm as the byte write setup. 7. a block lock-bit can be set while wp# is v ih . 8. wp# must be at v ih to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. 9. following the third bus cycle, inputs the write address and write data of ?n? times. finally, input the confirm command ?d0h?. 10. commands other than those shown above are reserved by sharp for future device implementations and should not be used. lhf16ktv 11 rev. 2.0 4.1 read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend and (multi) word/byte write suspend command. the read array command functions independently of the v pp voltage and rp# must be v ih . 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 4 retrieve the manufacturer, device, block lock configuration and block erase status (see table 5 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pp voltage and rp# must be v ih . following the read identifier codes command, the following information can be read: table 5. identifier codes code address data manufacture code 00000 00001 b0 device code 00002 00003 d0 block status code x0004 (1) x0005 (1) ? block is unlocked dq 0 =0 ? block is locked dq 0 =1 ? last erase operation completed successfully dq 1 =0 ? last erase operation did not completed successfully dq 1 =1 ? reserved for future use dq 2-7 note: 1. x selects the specific block status code to be read. see figure 4 for the device identifier code memory map. 4.3 read status register command the status register may be read to determine when a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration is complete and whether the operation completed successfully(see table 14). it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or ce#(either ce 0 # or ce 1 #), whichever occurs. oe# or ce#(either ce 0 # or ce 1 #) must toggle to v ih before further reads to update the status register latch. the read status register command functions independently of the v pp voltage. rp# must be v ih . the extended status register may be read to determine multi word/byte write availability(see table 14.1). the extended status register may be read at any time by writing the multi word/byte write command. after writing this command, all subsequent read operations output data from the extended status register, until another valid command is written. multi word/byte write command must be re-issued to update the extended status register latch. 4.4 clear status register command status register bits sr.5, sr.4, sr.3 and sr.1 are set to "1"s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 14). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register may be polled to determine if an error occurs during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v pp voltage. rp# must be v ih . this command is not functional during block erase, full chip erase, (multi) word/byte write block lock-bit configuration, block erase suspend or (multi) word/byte write suspend modes. lhf16ktv 12 rev. 2.0 4.5 query command query database can be read by writing query command (98h). following the command write, read cycle from address shown in table 7~11 retrieve the critical information to write, erase and otherwise control the flash component. a 0 of query offset address is ignored when x8 mode (byte#=v il ). query data are always presented on the low-byte data output (dq 0 -dq 7 ). in x16 mode, high-byte (dq 8 -dq 15 ) outputs 00h. the bytes not assigned to any information or reserved for future use are set to "0". this command functions independently of the v pp voltage. rp# must be v ih . table 6. example of query structure output mode offset address output dq 15~8 dq 7~0 x8 mode a 5 , a 4 , a 3 , a 2 , a 1 , a 0 1 , 0 , 0 , 0 , 0 , 0 (20h) 1 , 0 , 0 , 0 , 0 , 1 (21h) 1, 0 , 0 , 0 , 1 , 0 (22h) 1 , 0 , 0 , 0 , 1 , 1 (23h) high z high z high z high z "q" "q" "r" "r" x16 mode a 5 , a 4 , a 3 , a 2 , a 1 1 , 0 , 0 , 0 , 0 (10h) 1 , 0 , 0 , 0 , 1 (11h) 00h 00h "q" "r" 4.5.1 block status register this field provides lock configuration and erase status for the specified block. these informations are only available when device is ready (sr.7=1). if block erase or full chip erase operation is finished irregulary, block erase status bit will be set to "1". if bit 1 is "1", this block is invalid. table 7. query block status register offset (word address) length description (ba+2)h 01h block status register bit0 block lock configuration 0=block is unlocked 1=block is locked bit1 block erase status 0=last erase operation completed successfully 1=last erase operation not completed successfully bit2-7 reserved for future use note: 1. ba=the beginning of a block address. lhf16ktv 13 rev. 2.0 4.5.2 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. additionally, it indicates which version of the spec and which vendor-specified command set(s) is(are) supported. table 8. cfi query identification string offset (word address) length description 10h,11h,12h 03h query unique ascii string "qry" 51h,52h,59h 13h,14h 02h primary vendor command set and control interface id code 01h,00h (scs id code) 15h,16h 02h address for primary algorithm extended query table 31h,00h (scs extended query table offset) 17h,18h 02h alternate vendor command set and control interface id code 0000h (0000h means that no alternate exists) 19h,1ah 02h address for alternate algorithm extended query table 0000h (0000h means that no alternate exists) 4.5.3 system interface information the following device information can be useful in optimizing system interface software. table 9. system information string offset (word address) length description 1bh 01h v cc logic supply minimum write/erase voltage 27h (2.7v) 1ch 01h v cc logic supply maximum write/erase voltage 55h (5.5v) 1dh 01h v pp programming supply minimum write/erase voltage 27h (2.7v) 1eh 01h v pp programming supply maximum write/erase voltage 55h (5.5v) 1fh 01h typical timeout per single byte/word write 03h (2 3 =8s) 20h 01h typical timeout for maximum size buffer write (32 bytes) 06h (2 6 =64s) 21h 01h typical timeout per individual block erase 0ah (0ah=10, 2 10 =1024ms) 22h 01h typical timeout for full chip erase 0fh (0fh=15, 2 15 =32768ms) 23h 01h maximum timeout per single byte/word write, 2 n times of typical. 04h (2 4 =16, 8sx16=128s) 24h 01h maximum timeout maximum size buffer write, 2 n times of typical. 04h (2 4 =16, 64sx16=1024s) 25h 01h maximum timeout per individual block erase, 2 n times of typical. 04h (2 4 =16, 1024msx16=16384ms) 26h 01h maximum timeout for full chip erase, 2 n times of typical. 04h (2 4 =16, 32768msx16=524288ms) lhf16ktv 14 rev. 2.0 4.5.4 device geometry definition this field provides critical details of the flash device geometry. table 10. device geometry definition offset (word address) length description 27h 01h device size 15h (15h=21, 2 21 =2097152=2m bytes) 28h,29h 02h flash device interface description 02h,00h (x8/x16 supports x8 and x16 via byte#) 2ah,2bh 02h maximum number of bytes in multi word/byte write 05h,00h (2 5 =32 bytes ) 2ch 01h number of erase block regions within device 01h (symmetrically blocked) 2dh,2eh 02h the number of erase blocks 1fh,00h (1fh=31 ==> 31+1=32 blocks) 2fh,30h 02h the number of "256 bytes" cluster in a erase block 00h,01h (0100h=256 ==>256 bytes x 256= 64k bytes in a erase block) 4.5.5 scs oem specific extended query table certain flash features and commands may be optional in a vendor-specific algorithm specification. the optional vendor-specific query table(s) may be used to specify this and other types of information. these structures are defined solely by the flash vendor(s). table 11. scs oem specific extended query table offset (word address) length description 31h,32h,33h 03h pri 50h,52h,49h 34h 01h 31h (1) major version number , ascii 35h 01h 30h (0) minor version number, ascii 36h,37h, 38h,39h 04h 0fh,00h,00h,00h optional command support bit0=1 : chip erase supported bit1=1 : suspend erase supported bit2=1 : suspend write supported bit3=1 : lock/unlock supported bit4=0 : queued erase not supported bit5-31=0 : reserved for future use 3ah 01h 01h supported functions after suspend bit0=1 : write supported after erase suspend bit1-7=0 : reserved for future use 3bh,3ch 02h 03h,00h block status register mask bit0=1 : block status register lock bit [bsr.0] active bit1=1 : block status register valid bit [bsr.1] active bit2-15=0 : reserved for future use 3dh 01h v cc logic supply optimum write/erase voltage(highest performance) 50h(5.0v) 3eh 01h v pp programming supply optimum write/erase voltage(highest performance) 50h(5.0v) 3fh reserved reserved for future versions of the scs specification lhf16ktv 15 rev. 2.0 4.6 block erase command block erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the output data of the sts pin or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable block erasure can only occur when v cc =v cc1/2 and v pp =v pph1/2/3 . in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". successful block erase requires that the corresponding block lock-bit be cleared or if set, that wp#=v ih . if block erase is attempted when the corresponding block lock-bit is set and wp#=v il , sr.1 and sr.5 will be set to "1". 4.7 full chip erase command this command followed by a confirm command (d0h) erases all of the unlocked blocks. a full chip erase setup is first written, followed by a full chip erase confirm. after a confirm command is written, device erases the all unlocked blocks from block 0 to block 31 block by block. this command sequence requires appropriate sequencing. block preconditioning, erase and verify are handled internally by the wsm (invisible to the system). after the two-cycle full chip erase sequence is written, the device automatically outputs status register data when read (see figure 6). the cpu can detect full chip erase completion by analyzing the output data of the sts pin or status register bit sr.7. when the full chip erase is complete, status register bit sr.5 should be checked. if erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. if error is detected on a block during full chip erase operation, wsm stops erasing. reading the block valid status by issuing read id codes command or query command informs which blocks failed to its erase. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid full chip erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable full chip erasure can only occur when v cc =v cc1/2 and v pp =v pph1/2/3 . in the absence of this high voltage, block contents are protected against erasure. if full chip erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". when wp#=v ih , all blocks are erased independent of block lock-bits status. when wp#=v il , only unlocked blocks are erased. in this case, sr.1 and sr.5 will not be set to "1". full chip erase can not be suspended. lhf16ktv 16 rev. 2.0 4.8 word/byte write command word/byte write is executed by a two-cycle command sequence. word/byte write setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the word/byte write and write verify algorithms internally. after the word/byte write sequence is written, the device automatically outputs status register data when read (see figure 7). the cpu can detect the completion of the word/byte write event by analyzing the sts pin or status register bit sr.7. when word/byte write is complete, status register bit sr.4 should be checked. if word/byte write error is detected, the status register should be cleared. the internal wsm verify only detects errors for "1"s that do not successfully write to "0"s. the cui remains in read status register mode until it receives another command. reliable word/byte writes can only occur when v cc =v cc1/2 and v pp =v pph1/2/3 . in the absence of this high voltage, memory contents are protected against word/byte writes. if word/byte write is attempted while v pp v pplk , status register bits sr.3 and sr.4 will be set to "1". successful word/byte write requires that the corresponding block lock-bit be cleared or, if set, that wp#=v ih . if word/byte write is attempted when the corresponding block lock-bit is set and wp#=v il , sr.1 and sr.4 will be set to "1". word/byte write operations with v il lhf16ktv 17 rev. 2.0 4.10 block erase suspend command the block erase suspend command allows block- erase interruption to read or (multi) word/byte-write data in another block of memory. once the block- erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bits sr.7 and sr.6 can determine when the block erase operation has been suspended (both will be set to "1"). sts will also transition to high z. specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. a (multi) word/byte write command sequence can also be issued during erase suspend to program data in other blocks. using the (multi) word/byte write suspend command (see section 4.11), a (multi) word/byte write operation can also be suspended. during a (multi) word/byte write operation with block erase suspended, status register bit sr.7 will return to "0" and the sts (if set to ry/by#) output will transition to v ol . however, sr.6 will remain "1" to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and sts will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read (see figure 10). v pp must remain at v pph1/2/3 (the same v pp level used for block erase) while block erase is suspended. rp# must also remain at v ih . wp# must also remain at the same level used for block erase. byte# must be the same level as writing the block erase command when the block erase resume command is written. block erase cannot resume until (multi) word/byte write operations initiated during block erase suspend have completed. 4.11 (multi) word/byte write suspend command the (multi) word/byte write suspend command allows (multi) word/byte write interruption to read data in other flash memory locations. once the (multi) word/byte write process starts, writing the (multi) word/byte write suspend command requests that the wsm suspend the (multi) word/byte write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the (multi) word/byte write suspend command is written. polling status register bits sr.7 and sr.2 can determine when the (multi) word/byte write operation has been suspended (both will be set to "1"). sts will also transition to high z. specification t whrh1 defines the (multi) word/byte write suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while (multi) word/byte write is suspended are read status register and (multi) word/byte write resume. after (multi) word/byte write resume command is written to the flash memory, the wsm will continue the (multi) word/byte write process. status register bits sr.2 and sr.7 will automatically clear and sts will return to v ol . after the (multi) word/byte write command is written, the device automatically outputs status register data when read (see figure 11). v pp must remain at v pph1/2/3 (the same v pp level used for (multi) word/byte write) while in (multi) word/byte write suspend mode. rp# must also remain at v ih . wp# must also remain at the same level used for (multi) word/byte write. byte# must be the same level as writing the (multi) word/byte write command when the (multi) word/byte write resume command is written. lhf16ktv 18 rev. 2.0 4.12 set block lock-bit command a flexible block locking and unlocking scheme is enabled via block lock-bits. the block lock-bits gate program and erase operations with wp#=v ih , individual block lock-bits can be set using the set block lock-bit command. see table 13 for a summary of hardware and software write protection options. set block lock-bit is executed by a two-cycle command sequence. the set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). the wsm then controls the set block lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see figure 12). the cpu can detect the completion of the set block lock-bit event by analyzing the sts pin output or status register bit sr.7. when the set block lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally set. an invalid set block lock-bit command will result in status register bits sr.4 and sr.5 being set to "1". also, reliable operations occur only when v cc =v cc1/2 and v pp =v pph1/2/3 . in the absence of this high voltage, block lock-bit contents are protected against alteration. a successful set block lock-bit operation requires wp#=v ih . if it is attempted with wp#=v il , sr.1 and sr.4 will be set to "1" and the operation will fail. set block lock-bit operations with wp# lhf16ktv 20 rev. 2.0 table 14. status register definition wsms bess ecblbs wsblbs vpps wss dps r 76543210 sr.7 = write state machine status 1 = ready 0 = busy sr.6 = block erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear block lock-bits status 1 = error in erase or clear blocl lock-bits 0 = successful erase or clear block lock-bits sr.4 = write and set block lock-bit status 1 = error in write or set block lock-bit 0 = successful write or set block lock-bit sr.3 = v pp status 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = write suspend status 1 = write suspended 0 = write in progress/completed sr.1 = device protect status 1 = block lock-bit and/or wp# lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements notes: check sts or sr.7 to determine block erase, full chip erase, (multi) word/byte write or block lock-bit configuration completion. sr.6-0 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, full chip erase, (multi) word/byte write, block lock-bit configuration or sts configuration attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. sr.3 is not guaranteed to reports accurate feedback only when v pp v pph1/2/3 . sr.1 does not provide a continuous indication of block lock-bit values. the wsm interrogates block lock-bit, and wp# only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set and/or wp# is not v ih . reading the block lock configuration codes after writing the read identifier codes command indicates block lock-bit status. sr.0 is reserved for future use and should be masked out when polling the status register. table 14.1. extended status register definition sms r r r r r r r 76543210 xsr.7 = state machine status 1 = multi word/byte write available 0 = multi word/byte write not available xsr.6-0=reserved for future enhancements notes: after issue a multi word/byte write command: xsr.7 indicates that a next multi word/byte write command is available. xsr.6-0 is reserved for future use and should be masked out when polling the extended status register. bus operation command comments write write read standby erase setup erase confirm data=20h addr=within block to be erased data=d0h addr=within block to be erased status register data check sr.7 1=wsm ready 0=wsm busy repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last operation to place device in read array mode. bus operation command comments standby 1=v pp error detect 1=device protect detect check sr.4,5 sr.5,sr.4,sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1=block erase error standby standby standby check sr.3 check sr.1 wp#=v il ,block lock-bit is set only required for systems implementing lock-bit configuration both 1=command sequence error full status check procedure read status register data(see above) sr.3= 1 0 v pp range error device protect error command sequence error block erase error sr.1= 1 0 sr.4,5= sr.5= 1 1 0 0 block erase successful start write 20h, block address write d0h, block address read status register sr.7= 0 1 suspend block erase no yes suspend block erase loop full status check if desired block erase complete write 70h read status register sr.7= 0 1 write read read status data=70h addr=x standby register status register data check sr.7 1=wsm ready 0=wsm busy lhf16ktv 21 rev. 2.0 figure 5. automated block erase flowchart bus operation command comments write write read standby full chip erase confirm data=30h addr=x data=d0h addr=x status register data check sr.7 1=wsm ready 0=wsm busy full status check can be done after each full chip erase. write ffh after the last operation to place device in read array mode. bus operation command comments standby 1=v pp error detect check sr.4,5 sr.5,sr.4,sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1=full chip erase error standby standby check sr.3 both 1=command sequence error full status check procedure read status register data(see above) sr.3= 1 0 v pp range error command sequence error full chip erase error sr.4,5= sr.5= 1 1 0 0 full chip erase successful start write 30h write d0h read status register sr.7= 0 1 full status check if desired full chip erase complete write 70h read status register sr.7= 0 1 write read read status data=70h addr=x standby register status register data check sr.7 1=wsm ready 0=wsm busy full chip erase setup lhf16ktv 22 rev. 2.0 figure 6. automated full chip erase flowchart bus operation command comments write write read standby setup word/byte word/byte write data=40h or 10h addr=location to be written data=data to be written addr=location to be written status register data check sr.7 1=wsm ready 0=wsm busy repeat for subsequent word/byte writes. sr full status check can be done after each word/byte write, or after a sequence of word/byte writes. write ffh after the last word/byte write operation to place device in read array mode. bus operation command comments 1=v pp error detect 1=device protect detect sr.4,sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.4 1=data write error standby standby standby check sr.3 check sr.1 wp#=v il ,block lock-bit is set only required for systems implementing lock-bit configuration start write 40h or 10h, address write word/byte data and address read status register sr.7= 0 1 suspend word/byte no yes suspend word/byte write loop full status check if desired word/byte write complete full status check procedure read status register data(see above) sr.3= 1 0 v pp range error device protect error word/byte write error sr.1= 1 0 sr.4= 1 0 word/byte write write 70h read status register sr.7= 0 1 write read read status data=70h addr=x standby register status register data check sr.7 1=wsm ready 0=wsm busy write successful write lhf16ktv 23 rev. 2.0 figure 7. automated word/byte write flowchart bus operation command comments write write data=word or byte count (n)-1 addr=start address data=buffer data addr=start address check sr.7 1=wsm ready 0=wsm busy sr full status check can be done after each multi word/byte write, or after a sequence of multi word/byte writes. write ffh after the last multi word/byte write operation to place device in read array mode. start write word or byte count (n)-1, start address write buffer data, start address x=1 0 suspend multi word/byte no yes suspend multi word/byte write loop full status check if desired write e8h, read extend status register xsr.7= 0 1 write read data=e8h addr=start address standby extended status register data check xsr.7 1=multi word/byte write ready 0=multi word/byte write busy start address x=x+1 write d0h another write ? buffer read status register sr.7= 1 complete no yes multi word/byte write write data=buffer data addr=device address standby write read data=d0h addr=x status register data 1. byte or word count values on dq 0-7 are loaded into the count register. 2. write buffer contents will be programmed at the start address. 3. align the start address on a write buffer boundary for maximum programming performance. 4.the device aborts the multi word/byte write command if the current address is outside of the original block address. 5.the status register indicates an "improper command sequence" if the multi word/byte command is aborted. follow this with a clear status register command. (note2,3) (note1) (note4,5) multi word/byte write write buffer time out no yes setup write x = n yes no write buffer data, device address abort buffer write commnad? write another block address abort multi word/byte write no yes lhf16ktv 24 rev. 2.0 figure 8. automated multi word/byte write flowchart bus operation command comments 1=v pp error detect 1=device protect detect sr.5,sr.4,sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.4 1=data write error standby standby standby check sr.3 check sr.1 wp#=v il ,block lock-bit is set only required for systems implementing lock-bit configuration full status check procedure for read status register sr.3= 1 0 v pp range error device protect error multi word/byte write sr.1= 1 0 sr.4= 1 0 multi word/byte write command sequence sr.4,5= 1 0 error multi word/byte write operation successful check sr.4,5 both 1=command sequence error standby error lhf16ktv 25 rev. 2.0 figure 9. full status check procedure for automated multi word/byte write start write b0h (multi) word/byte write loop read status register sr.7= 0 1 no bus operation command comments write read standby data=b0h addr=x data=d0h status register data check sr.7 1=wsm ready 0=wsm busy yes sr.6= 0 1 read array data done? block erase resumed read array data block erase completed write ffh write d0h standby write erase suspend erase resume addr=x addr=x check sr.6 1=block erase suspended 0=block erase completed read or write ? read (multi) word/byte write lhf16ktv 26 rev. 2.0 figure 10. block erase suspend/resume flowchart start write b0h write ffh read status register sr.7= 0 1 no bus operation command comments write read standby data=b0h addr=x data=d0h status register data check sr.7 1=wsm ready 0=wsm busy yes sr.2= 0 1 read array data done reading (multi) word/byte write read array data (multi) word/byte write write ffh write d0h standby write write read (multi) word/byte write suspend read array (multi) word/byte write resume addr=x addr=x data=ffh addr=x check sr.2 1=(multi) word/byte write 0=(multi) word/byte write read array locations other than that being written. completed resumed suspended completed lhf16ktv 27 rev. 2.0 figure 11. (multi) word/byte write suspend/resume flowchart start write 60h, block address write 01h, block address read status register sr.7= 0 1 full status check if desired complete set block lock-bit full status check procedure read status register data(see above) sr.3= 1 0 v pp range error device protect error command sequence error set block lock-bit error sr.1= 1 0 sr.4,5= sr.4= 1 1 0 0 set block lock-bit bus operation command comments write write read standby data=60h addr=block address data=01h, addr=block address status register data check sr.7 1=wsm ready 0=wsm busy repeat for subsequent block lock-bit set operations. full status check can be done after each block lock-bit set operation or after a sequence of block lock-bit set operations. write ffh after the last block lock-bit set operation to place device in read array mode. set block lock-bit setup set block lock-bit confirm bus operation command comments standby 1=v pp error detect 1=device protect detect check sr.4,5 sequence error sr.5,sr.4,sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple block lock-bits are set before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.4 1=set block lock-bit error standby standby standby check sr.3 check sr.1 wp#=v il both 1=command successful lhf16ktv 28 rev. 2.0 figure 12. set block lock-bit flowchart start write 60h write d0h read status register sr.7= 0 1 full status check if desired complete clear block lock-bits full status check procedure read status register data(see above) sr.3= 1 0 v pp range error device protect error command sequence error clear block lock-bits sr.1= 1 0 sr.4,5= sr.5= 1 1 0 0 clear block lock-bits error successful bus operation command comments write write read standby data=60h addr=x data=d0h addr=x status register data check sr.7 1=wsm ready 0=wsm busy write ffh after the clear block lock-bits operation to place device in read array mode. clear block lock-bits setup clear block lock-bits confirm bus operation command comments standby 1=v pp error detect 1=device protect detect check sr.4,5 sequence error sr.5,sr.4,sr.3 and sr.1 are only cleared by the clear status register command. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1=clear block lock-bits error standby standby standby check sr.3 check sr.1 both 1=command wp#=v il lhf16ktv 29 rev. 2.0 figure 13. clear block lock-bits flowchart lhf16ktv 30 rev. 2.0 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three- line control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the system?s read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 sts and block erase, full chip erase, (multi) word/byte write and block lock-bit configuration polling sts is an open drain output that should be connected to v cc by a pullup resistor to provide a hardware method of detecting block erase, full chip erase, (multi) word/byte write and block lock-bit configuration completion. in default mode, it transitions low after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration commands and returns to v oh when the wsm has finished executing the internal algorithm. for alternate sts pin configurations, see the configuration command. sts can be connected to an interrupt input of the system cpu or controller. it is active at all times. sts, in default mode, is also high z when the device is in block erase suspend (with (multi) word/byte write inactive), (multi) word/byte write suspend or deep power-down modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1f ceramic capacitor connected between its v cc and gnd and between its v pp and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7f electrolytic capacitor should be placed at the array?s power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 v pp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. use similar trace widths and layout considerations given to the v cc power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. lhf16ktv 31 rev. 2.0 5.5 v cc , v pp , rp# transitions block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if v pp falls outside of a valid v pph1/2/3 range, v cc falls outside of a valid v cc1/2 range, or rp#=v il . if v pp error is detected, status register bit sr.3 is set to "1" along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v il during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, sts(if set to ry/by# mode) will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v il clear the status register. the cui latches commands issued by system software and is not altered by v pp or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from deep power-down or after v cc transitions below v lko . after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, even after v pp transitions down to v pplk , the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. 5.6 power-up/down protection the device is designed to offer protection against accidental block and full chip erasure, (multi) word/byte writing or block lock-bit configuration during power transitions. upon power-up, the device is indifferent as to which power supply (v pp or v cc ) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we# and ce# must be low for a command write, driving either to v ih will inhibit writes. the cui?s two-step command sequence architecture provides added level of protection against data alteration. in-system block lock and unlock capability prevents inadvertent data alteration. the device is disabled while rp#=v il regardless of its control inputs state. 5.7 power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memory?s nonvolatility increases usable battery life because data is retained when system power is removed. in addition, deep power-down mode ensures extremely low power consumption even when system power is applied. for example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering rp# to v il standby or sleep modes. if access is again needed, the devices can be read following the t phqv and t phwl wake-up cycles required after rp# is first raised to v ih . see ac characteristics ? read only and write operations and figures 17, 18, 19, 20 for more information. lhf16ktv 32 rev. 2.0 6 electrical specifications 6.1 absolute maximum ratings* operating temperature during read, erase, write and block lock-bit configuration .....-40c to +85c (1) temperature under bias ............... -40c to +85c storage temperature ........................ -65c to +125c voltage on any pin (except v cc , v pp )............... -0.5v to v cc +0.5v (2) v cc suply voltage ............................-0.2v to +7.0v (2) v pp update voltage during erase, write and block lock-bit configuration ......-0.2v to +7.0v (2) output short circuit current ........................ 100ma (3) *warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes: 1. operating temperature is for extended temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v cc and v pp pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins and v cc is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 6.2 operating conditions temperature and v cc operating conditions symbol parameter min. max. unit test condition t a operating temperature -40 +85 c ambient temperature v cc1 v cc supply voltage (2.7v-3.6v) 2.7 3.6 v v cc2 v cc supply voltage (3.3v0.3v) 3.0 3.6 v 6.2.1 capacitance (1) t a =+25c, f=1mhz symbol parameter typ. max. unit condition c in input capacitance 7 10 pf v in =0.0v c out output capacitance 9 12 pf v out =0.0v note: 1. sampled, not 100% tested. ac test inputs are driven at 2.7v for a logic "1" and 0.0v for a logic "0." input timing begins, and output timing ends, at 1.3 5v. input rise and fall times (10% to 90%) <10 ns. 2.7 0.0 input test points output 1.35 1.35 ac test inputs are driven at 3.0v for a logic "1" and 0.0v for a logic "0." input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) <10 ns. 3.0 0.0 input test points output 1.5 1.5 1.3v 1n914 device under test c l out c l includes jig r l =3.3k ? capacitance lhf16ktv 33 rev. 2.0 6.2.2 ac input/output test conditions figure 14. transient input/output reference waveform for v cc =2.7v-3.6v figure 15. transient input/output reference waveform for v cc =3.3v0.3v test configuration capacitance loading value test configuration c l (pf) v cc =3.3v0.3v, 2.7v-3.6v 50 figure 16. transient equivalent testing load circuit lhf16ktv 34 rev. 2.0 6.2.3 dc characteristics dc characteristics v cc =2.7v v cc =3.3v test sym. parameter notes typ. max. typ. max. unit conditions i li input load current 1 0.5 0.5 a v cc =v cc max. v in =v cc or gnd i lo output leakage current 1 0.5 0.5 a v cc =v cc max. v out =v cc or gnd i ccs v cc standby current 1,3,6 20 100 20 100 a cmos inputs v cc =v cc max. ce#=rp#=v cc 0.2v 1 4 1 4 ma ttl inputs v cc =v cc max. ce#=rp#=v ih i ccd v cc deep power-down current 1 20 20 a rp#=gnd0.2v i out (sts)=0ma i ccr v cc read current 1,5,6 25 25 ma cmos inputs v cc =v cc max. ce#=gnd f=5mhz, i out =0ma 30 30 ma ttl inputs v cc =v cc max., ce#=v il f=5mhz, i out =0ma i ccw v cc write current 1,7 17 ? ? ma v pp =2.7v-3.6v ((multi) w/b write or 17 17 ma v pp =3.3v0.3v set block lock bit) 17 17 ma v pp =5.0v0.5v i cce v cc erase current 1,7 17 ? ? ma v pp =2.7v-3.6v (block erase, full chip 17 17 ma v pp =3.3v0.3v erase, clear block lock bits) 17 17 ma v pp =5.0v0.5v i ccws i cces v cc write or block erase suspend current 1,2 1 6 1 6 ma ce#=v ih i pps v pp standby current 1 2 15 2 15 a v pp v cc i ppr v pp read current 1 10 200 10 200 a v pp >v cc i ppd v pp deep power-down current 1 0.1 5 0.1 5 a rp#=gnd0.2v i ppw v pp write current 1,7 80 ? ? ma v pp =2.7v-3.6v ((multi) w/b write or 80 80 ma v pp =3.3v0.3v set block lock bit) 80 80 ma v pp =5.0v0.5v i ppe v pp erase current 1,7 40 ? ? ma v pp =2.7v-3.6v (block erase, full chip 40 40 ma v pp =3.3v0.3v erase, clear block lock bits) 40 40 ma v pp =5.0v0.5v i ppws i ppes v pp write or block erase suspend current 1 10 200 10 200 a v pp =v pph1/2/3 lhf16ktv 35 rev. 2.0 dc characteristics (continued) v cc =2.7v v cc =3.3v test sym. parameter notes min. max. min. max. unit conditions v il input low voltage 7 -0.5 0.8 -0.5 0.8 v v ih input high voltage 7 2.0 v cc +0.5 2.0 v cc +0.5 v v ol output low voltage 3,7 0.4 0.4 v v cc =v cc min. i ol =2ma v oh1 output high voltage (ttl) 3,7 2.4 2.4 v v cc =v cc min. i oh =-2.5ma v oh2 output high voltage (cmos) 3,7 0.85 v cc 0.85 v cc v v cc =v cc min. i oh =-2.5ma v cc -0.4 v cc -0.4 v v cc =v cc min. i oh =-100a v pplk v pp lockout voltage during normal operations 4,7 1.5 1.5 v v pph1 v pp voltage during write or erase operations 2.7 3.6 ? ? v v pph2 v pp voltage during write or erase operations 3.0 3.6 3.0 3.6 v v pph3 v pp voltage during write or erase operations 4.5 5.5 4.5 5.5 v v lko v cc lockout voltage 2.0 2.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a =+25c. 2. i ccws and i cces are specified with the device de-selected. if read or byte written while in erase suspend mode, the device?s current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 3. includes sts. 4. block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph1 (min.), between v pph1 (max.) and v pph2 (min.), between v pph2 (max.) and v pph3 (min.) and above v pph3 (max.). 5. automatic power savings (aps) reduces typical i ccr to 3ma at 2.7v and 3.3v v cc in static operation. 6. cmos inputs are either v cc 0.2v or gnd0.2v. ttl inputs are either v il or v ih . 7. sampled, not 100% tested. lhf16ktv 36 rev. 2.0 6.2.4 ac characteristics - read-only operations (1) v cc =2.7v-3.6v, t a =-40c to +85c versions (4) lh28f160s3h-l120 sym. parameter notes min. max. unit t avav read cycle time 120 ns t avqv address to output delay 120 ns t elqv ce# to output delay 2 120 ns t phqv rp# high to output delay 600 ns t glqv oe# to output delay 2 50 ns t elqx ce# to output in low z 3 0 ns t ehqz ce# high to output in high z 3 50 ns t glqx oe# to output in low z 3 0 ns t ghqz oe# high to output in high z 3 20 ns t oh output hold from address, ce# or oe# change, whichever occurs first 3 0 ns t flqv t fhqv byte# to output delay 3 120 ns t flqz byte# to output in high z 3 30 ns t elfl t elfh ce# low to byte# high or low 3 5 ns note: see 3.3v v cc read-only operations for notes 1 through 4. v cc =3.3v0.3v, t a =-40c to +85c versions (4) lh28f160s3h-l100 sym. parameter notes min. max. unit t avav read cycle time 100 ns t avqv address to output delay 100 ns t elqv ce# to output delay 2 100 ns t phqv rp# high to output delay 600 ns t glqv oe# to output delay 2 45 ns t elqx ce# to output in low z 3 0 ns t ehqz ce# high to output in high z 3 50 ns t glqx oe# to output in low z 3 0 ns t ghqz oe# high to output in high z 3 20 ns t oh output hold from address, ce# or oe# change, whichever occurs first 3 0 ns t flqv t fhqv byte# to output delay 3 100 ns t flqz byte# to output in high z 3 30 ns t elfl t elfh ce# low to byte# high or low 3 5 ns notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. 4. see ordering information for device speeds (valid operational combinations). addresses(a) ce#(e) oe#(g) we#(w) data(d/q) rp#(p) v cc standby device address selection data valid address stable t avav t ehqz t ghqz high z valid output t glqv t elqv t glqx t elqx t avqv t phqv high z t oh v il v oh v ol v ih v ih v ih v ih v ih v il v il v il v il note: ce# is defined as the latter of ce 0 # and ce 1 # going low or the first of ce 0 # or ce 1 # going high. lhf16ktv 37 rev. 2.0 figure 17. ac waveform for read operations addresses(a) ce#(e) oe#(g) byte#(f) data(d/q) standby device address selection data valid address stable t avav t ehqz t ghqz high z data output t glqv t elqv t glqx t elqx t avqv high z t oh v il v oh v ol v ih v ih v ih v ih v il v il v il note: ce# is defined as the latter of ce 0 # and ce 1 # going low or the first of ce 0 # or ce 1 # going high. valid output data(d/q) high z t avfl = t elfl high z v oh v ol data output (dq 0 -dq 7 ) (dq 8 -dq 15 ) t elfl t flqv = t avqv t flqz lhf16ktv 38 rev. 2.0 figure 18. byte# timing waveforms lhf16ktv 39 rev. 2.0 6.2.5 ac characteristics - write operations (1) v cc =2.7v-3.6v, t a =-40c to +85c versions (5) lh28f160s3h-l120 sym. parameter notes min. max. unit t avav write cycle time 120 ns t phwl rp# high recovery to we# going low 2 1 s t elwl ce# setup to we# going low 10 ns t wlwh we# pulse width 50 ns t shwh wp# v ih setup to we# going high 2 100 ns t vpwh v pp setup to we# going high 2 100 ns t avwh address setup to we# going high 3 50 ns t dvwh data setup to we# going high 3 50 ns t whdx data hold from we# high 5 ns t whax address hold from we# high 5 ns t wheh ce# hold from we# high 10 ns t whwl we# pulse width high 30 ns t whrl we# high to sts going low 100 ns t whgl write recovery before read 0 ns t qvvl v pp hold from valid srd, sts high z 2,4 0 ns t qvsl wp# v ih hold from valid srd, sts high z 2,4 0 ns t fvwh byte# setup to we# going high 50 ns t whfv byte# hold from we# high note 6 ns note: see 3.3v v cc we#-controlled writes for notes 1 through 6. lhf16ktv 40 rev. 2.0 v cc =3.3v0.3v, t a =-40c to +85c versions (5) lh28f160s3h-l100 sym. parameter notes min. max. unit t avav write cycle time 100 ns t phwl rp# high recovery to we# going low 2 1 s t elwl ce# setup to we# going low 10 ns t wlwh we# pulse width 50 ns t shwh wp# v ih setup to we# going high 2 100 ns t vpwh v pp setup to we# going high 2 100 ns t avwh address setup to we# going high 3 50 ns t dvwh data setup to we# going high 3 50 ns t whdx data hold from we# high 5 ns t whax address hold from we# high 5 ns t wheh ce# hold from we# high 10 ns t whwl we# pulse width high 30 ns t whrl we# high to sts going low 100 ns t whgl write recovery before read 0 ns t qvvl v pp hold from valid srd, sts high z 2,4 0 ns t qvsl wp# v ih hold from valid srd, sts high z 2,4 0 ns t fvwh byte# setup to we# going high 50 ns t whfv byte# hold from we# high note 6 ns notes: 1. read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 4 for valid a in and d in for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. v pp should be held at v pph1/2/3 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (sr.1/3/4/5=0). 5. see ordering information for device speeds (valid operational combinations). 6. byte# should be in stable until determination of block erase, full chip erase, (multi) word/byte write, block lock- bit configuration or sts configuration success (sr.7=1). v il v ih high z v ih v ih v ih v il v il v il v ol v il v ih v il v pplk v pph3,2,1 v ih v il notes: 1. v cc power-up and standby. 2. write each setup command. 3. write each confirm command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. addresses(a) ce#(e) oe#(g) we#(w) data(d/q) rp#(p) v pp (v) sts(r) } } } } } } 12 3 4 5 6 a in a in t avav t avwh t whax t elwl t wheh t whgl t whwl t whqv1,2,3,4 t wlwh t dvwh t whdx valid srd t phwl t whrl t vpwh t qvvl d in d in high z d in wp#(s) v ih v il t shwh t qvsl v ih v il byte#(f) t fvwh t whfv 7. ce# is defined as the latter of ce 0 # and ce 1 # going low or the first of ce 0 # or ce 1 # going high. lhf16ktv 41 rev. 2.0 figure 19. ac waveform for we#-controlled write operations lhf16ktv 42 rev. 2.0 6.2.6 alternative ce#-controlled writes (1) v cc =2.7v-3.6v, t a =-40c to +85c versions (5) lh28f160s3h-l120 sym. parameter notes min. max. unit t avav write cycle time 120 ns t phel rp# high recovery to ce# going low 2 1 s t wlel we# setup to ce# going low 0 ns t eleh ce# pulse width 70 ns t sheh wp# v ih setup to ce# going high 2 100 ns t vpeh v pp setup to ce# going high 2 100 ns t aveh address setup to ce# going high 3 50 ns t dveh data setup to ce# going high 3 50 ns t ehdx data hold from ce# high 5 ns t ehax address hold from ce# high 5 ns t ehwh we# hold from ce# high 0 ns t ehel ce# pulse width high 25 ns t ehrl ce# high to sts going low 100 ns t ehgl write recovery before read 0 ns t qvvl v pp hold from valid srd, sts high z 2,4 0 ns t qvsl wp# v ih hold from valid srd, sts high z 2,4 0 ns t fveh byte# setup to ce# going high 50 ns t ehfv byte# hold from ce# high note 6 ns note: see 3.3v v cc alternative ce#-controlled writes for notes 1 through 6. lhf16ktv 43 rev. 2.0 v cc =3.3v0.3v, t a =-40c to +85c versions (5) lh28f160s3h-l100 sym. parameter notes min. max. unit t avav write cycle time 100 ns t phel rp# high recovery to ce# going low 2 1 s t wlel we# setup to ce# going low 0 ns t eleh ce# pulse width 70 ns t sheh wp# v ih setup to ce# going high 2 100 ns t vpeh v pp setup to ce# going high 2 100 ns t aveh address setup to ce# going high 3 50 ns t dveh data setup to ce# going high 3 50 ns t ehdx data hold from ce# high 5 ns t ehax address hold from ce# high 5 ns t ehwh we# hold from ce# high 0 ns t ehel ce# pulse width high 25 ns t ehrl ce# high to sts going low 100 ns t ehgl write recovery before read 0 ns t qvvl v pp hold from valid srd, sts high z 2,4 0 ns t qvsl wp# v ih hold from valid srd, sts high z 2,4 0 ns t fveh byte# setup to ce# going high 50 ns t ehfv byte# hold from ce# high note 6 ns notes: 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 4 for valid a in and d in for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. v pp should be held at v pph1/2/3 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (sr.1/3/4/5=0). 5. see ordering information for device speeds (valid operational combinations). 6. byte# should be in stable until determination of block erase, full chip erase, (multi) word/byte write, block lock- bit configuration or sts configuration success (sr.7=1). v il v ih high z v ih v il v ol v il v ih v il v pplk v pph3,2,1 v ih v il notes: 1. v cc power-up and standby. 2. write each setup command. 3. write each confirm command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. addresses(a) oe#(g) data(d/q) rp#(p) v pp (v) sts(r) a in a in t avav t aveh t ehax t ehgl t ehdx valid srd t phel t ehrl t vpeh t qvvl d in d in high z d in } } } } } } 1 2 3 4 5 6 v ih v il wp#(s) t sheh t qvsl v ih v il byte#(f) t fveh t ehfv v ih v il we#(w) t wlel t ehwh t ehqv1,2,3,4 t dveh v ih v il ce#(e) t ehel t eleh 7. ce# is defined as the latter of ce 0 # and ce 1 # going low or the first of ce 0 # or ce 1 # going high. lhf16ktv 44 rev. 2.0 figure 20. ac waveform for ce#-controlled write operations rp#(p) v il t plph t plrh (a)reset during read array mode (b)reset during block erase, full chip erase, (multi) word/byte write v ih high z v ih high z v ol v il v ol t plph sts(r) sts(r) rp#(p) v il v ih rp#(p) t 23vph v il v cc 2.7/3.3v or block lock-bit configuretion (c)v cc power up timing lhf16ktv 45 rev. 2.0 6.2.7 reset operations figure 21. ac waveform for reset operation reset ac specifications v cc =2.7v v cc =3.3v symbol parameter notes min. max. min. max. unit t plph rp# pulse low time (if rp# is tied to v cc , this specification is not applicable) 100 100 ns t plrh rp# low to reset during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration 1,2 21.5 21.1 s t 23vph v cc at 2.7v to rp# high v cc at 3.0v to rp# high 3 100 100 ns notes: 1. if rp# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is not executing, the reset will complete within 100ns. 2. a reset time, t phqv , is required from the latter of sts going high z or rp# going high until outputs are valid. 3. when the device power-up, holding rp# low minimum 100ns is required after v cc has been in predefined range and also has been in stable there. lhf16ktv 46 rev. 2.0 6.2.8 block erase, full chip erase, (multi) word/byte write and block lock-bit configuration performance (3) v cc =2.7v-3.6v, t a =-40c to +85c v pp =2.7v-3.6v v pp =3.0v-3.6v v pp =4.5v-5.5v sym. parameter notes typ. (1) max. typ. (1) max. typ. (1) max. unit t whqv1 t ehqv1 word/byte write time (using w/b write, in word mode) 2 22.19 250 22.19 250 13.2 180 s t whqv1 t ehqv1 word/byte write time (using w/b write, in byte mode) 2 19.9 250 19.9 250 13.2 180 s word/byte write time (using multi word/byte write) 2 5.76 250 5.76 250 2.76 180 s block write time (using w/b write, in word mode) 2 0.73 8.2 0.73 8.2 0.44 4.8 s block write time (using w/b write, in byte mode) 2 1.31 16.5 1.31 16.5 0.87 10.9 s block write time (using multi word/byte write) 2 0.37 4.1 0.37 4.1 0.18 2 s t whqv2 t ehqv2 block erase time 2 0.56 10 0.56 10 0.42 10 s full chip erase time 17.9 320 17.9 320 13.4 320 s t whqv3 t ehqv3 set block lock-bit time 2 22.17 250 22.17 250 13.2 180 s t whqv4 t ehqv4 clear block lock-bits time 2 0.56 10 0.56 10 0.42 10 s t whrh1 t ehrh1 write suspend latency time to read 7.24 10.2 7.24 10.2 6.73 9.48 s t whrh2 t ehrh2 erase suspend latency time to read 15.5 21.5 15.5 21.5 12.54 17.54 s note: see 3.3v v cc block erase, full chip erase, (multi) word/byte write and block lock-bit configuration performance for notes 1 through 3. lhf16ktv 47 rev. 2.0 v cc =3.3v0.3v, t a =-40c to +85c v pp =3.0v-3.6v v pp =4.5v-5.5v sym. parameter notes typ. (1) max. typ. (1) max. unit t whqv1 t ehqv1 word/byte write time (using w/b write, in word mode) 2 21.75 250 12.95 180 s t whqv1 t ehqv1 word/byte write time (using w/b write, in byte mode) 2 19.51 250 12.95 180 s word/byte write time (using multi word/byte write) 2 5.66 250 2.7 180 s block write time (using w/b write, in word mode) 2 0.72 8.2 0.43 4.8 s block write time (using w/b write, in byte mode) 2 1.28 16.5 0.85 10.9 s block write time (using multi word/byte write) 2 0.36 4.1 0.18 2 s t whqv2 t ehqv2 block erase time 2 0.55 10 0.41 10 s full chip erase time 17.6 320 13.1 320 s t whqv3 t ehqv3 set block lock-bit time 2 21.75 250 12.95 180 s t whqv4 t ehqv4 clear block lock-bits time 2 0.55 10 0.41 10 s t whrh1 t ehrh1 write suspend latency time to read 7.1 10 6.6 9.3 s t whrh2 t ehrh2 erase suspend latency time to read 15.2 21.1 12.3 17.2 s notes: 1. typical values measured at t a =+25c and nominal voltages. assumes corresponding block lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. sampled but not 100% tested. lh 28 f 160 s 3 - hns tv product line designator for all sharp flash products device density 160 = 16-mbit power supply type 3 = smart 3 technology architecture s = regular block package t = 56-lead tsop r = 56-lead tsop(reverse bend) operating temperature h = -40c ~ +85c access speed (ns) 10:100ns (3.3v), 120ns (2.7v) 13:130ns (3.3v), 150ns (2.7v) b = 64-ball csp ns = 56-lead ssop blank = 0c ~ +70c d = 64-lead sdip lhf16ktv 48 rev. 2.0 7 additional information 7.1 ordering information valid operational combinations option order code v cc =2.7v-3.6v 50pf load, 1.35v i/o levels v cc =3.3v0.3v 50pf load, 1.5v i/o levels 1 LH28F160S3HNS-TV lh28f160s3h-l120 lh28f160s3h-l100 rev. 1.10 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1. ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?electrical specifications? described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page. t 2vph *1 v cc gnd v cc (min) rp# v il v ih (p) t phqv v ccw *2 gnd v ccwh1/2 (v) ce# v il v ih (e) we# v il v ih (w) oe# v il v ih (g) wp# v il v ih (s) v oh v ol (d/q) data high z valid output t vr t f t r t elqv t f t glqv (a) address valid (rst#) (v pp ) t r or t f address v il v ih t avqv *1 t 5vph for the device in 5v operations. t r or t f t r t r *2 to prevent the unwanted writes, system designers should consider the v ccw (v pp ) switch, which connects v ccw (v pp ) to gnd during read operations and v ccwh1/2 (v pph1/2 ) during write or erase operations. (v pph1/2 ) see the application note ap-007-sw-e for details. rev. 1.10 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. t r (max.) and t f (max.) for rp# (rst#) are 100 s/v. symbol parameter notes min. max. unit t vr v cc rise time 1 0.5 30000 s/v t r input signal rise time 1, 2 1 s/v t f input signal fall time 1, 2 1 s/v rev. 1.10 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2. waveform for glitch noises see the ? dc characteristics ? described in specifications for v ih (min.) and v il (max.). (a) acceptable glitch noises input signal v ih (min.) input signal v ih (min.) input signal v il (max.) input signal v il (max.) (b) not acceptable glitch noises rev. 1.10 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . s u g g e s t e d a p p l i c a t i o n s ( i f a n y ) a r e f o r s t a n d a r d u s e ; s e e i m p o r t a n t r e s t r i c t i o n s f o r l i m i t a t i o n s o n s p e c i a l a p p l i c a t i o n s . s e e l i m i t e d w a r r a n t y f o r s h a r p ? s p r o d u c t w a r r a n t y . t h e l i m i t e d w a r r a n t y i s i n l i e u , a n d e x c l u s i v e o f , a l l o t h e r w a r r a n t i e s , e x p r e s s o r i m p l i e d . a l l e x p r e s s a n d i m p l i e d w a r r a n t i e s , i n c l u d i n g t h e w a r r a n t i e s o f m e r c h a n t a b i l i t y , f i t n e s s f o r u s e a n d f i t n e s s f o r a p a r t i c u l a r p u r p o s e , a r e s p e c i f i c a l l y e x c l u d e d . i n n o e v e n t w i l l s h a r p b e l i a b l e , o r i n a n y w a y r e s p o n s i b l e , f o r a n y i n c i d e n t a l o r c o n s e q u e n t i a l e c o n o m i c o r p r o p e r t y d a m a g e . n o r t h a m e r i c a e u r o p e j a p a n s h a r p m i c r o e l e c t r o n i c s o f t h e a m e r i c a s 5 7 0 0 n w p a c i f i c r i m b l v d . c a m a s , w a 9 8 6 0 7 , u . s . a . p h o n e : ( 1 ) 3 6 0 - 8 3 4 - 2 5 0 0 f a x : ( 1 ) 3 6 0 - 8 3 4 - 8 9 0 3 f a s t i n f o : ( 1 ) 8 0 0 - 8 3 3 - 9 4 3 7 w w w . s h a r p s m a . c o m s h a r p m i c r o e l e c t r o n i c s e u r o p e d i v i s i o n o f s h a r p e l e c t r o n i c s ( e u r o p e ) g m b h s o n n i n s t r a s s e 3 2 0 0 9 7 h a m b u r g , g e r m a n y p h o n e : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 8 6 f a x : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 3 2 w w w . s h a r p s m e . c o m s h a r p c o r p o r a t i o n e l e c t r o n i c c o m p o n e n t s & d e v i c e s 2 2 - 2 2 n a g a i k e - c h o , a b e n o - k u o s a k a 5 4 5 - 8 5 2 2 , j a p a n p h o n e : ( 8 1 ) 6 - 6 6 2 1 - 1 2 2 1 f a x : ( 8 1 ) 6 1 1 7 - 7 2 5 3 0 0 / 6 1 1 7 - 7 2 5 3 0 1 w w w . s h a r p - w o r l d . c o m t a i w a n s i n g a p o r e k o r e a s h a r p e l e c t r o n i c c o m p o n e n t s ( t a i w a n ) c o r p o r a t i o n 8 f - a , n o . 1 6 , s e c . 4 , n a n k i n g e . r d . t a i p e i , t a i w a n , r e p u b l i c o f c h i n a p h o n e : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 4 1 f a x : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 2 6 / 2 - 2 5 7 7 - 7 3 2 8 s h a r p e l e c t r o n i c s ( s i n g a p o r e ) p t e . , l t d . 4 3 8 a , a l e x a n d r a r o a d , # 0 5 - 0 1 / 0 2 a l e x a n d r a t e c h n o p a r k , s i n g a p o r e 1 1 9 9 6 7 p h o n e : ( 6 5 ) 2 7 1 - 3 5 6 6 f a x : ( 6 5 ) 2 7 1 - 3 8 5 5 s h a r p e l e c t r o n i c c o m p o n e n t s ( k o r e a ) c o r p o r a t i o n r m 5 0 1 g e o s u n g b / d , 5 4 1 d o h w a - d o n g , m a p o - k u s e o u l 1 2 1 - 7 0 1 , k o r e a p h o n e : ( 8 2 ) 2 - 7 1 1 - 5 8 1 3 ~ 8 f a x : ( 8 2 ) 2 - 7 1 1 - 5 8 1 9 c h i n a h o n g k o n g s h a r p m i c r o e l e c t r o n i c s o f c h i n a ( s h a n g h a i ) c o . , l t d . 2 8 x i n j i n q i a o r o a d k i n g t o w e r 1 6 f p u d o n g s h a n g h a i , 2 0 1 2 0 6 p . r . c h i n a p h o n e : ( 8 6 ) 2 1 - 5 8 5 4 - 7 7 1 0 / 2 1 - 5 8 3 4 - 6 0 5 6 f a x : ( 8 6 ) 2 1 - 5 8 5 4 - 4 3 4 0 / 2 1 - 5 8 3 4 - 6 0 5 7 h e a d o f f i c e : n o . 3 6 0 , b a s h e n r o a d , x i n d e v e l o p m e n t b l d g . 2 2 w a i g a o q i a o f r e e t r a d e z o n e s h a n g h a i 2 0 0 1 3 1 p . r . c h i n a e m a i l : s m c @ c h i n a . g l o b a l . s h a r p . c o . j p s h a r p - r o x y ( h o n g k o n g ) l t d . 3 r d b u s i n e s s d i v i s i o n , 1 7 / f , a d m i r a l t y c e n t r e , t o w e r 1 1 8 h a r c o u r t r o a d , h o n g k o n g p h o n e : ( 8 5 2 ) 2 8 2 2 9 3 1 1 f a x : ( 8 5 2 ) 2 8 6 6 0 7 7 9 w w w . s h a r p . c o m . h k s h e n z h e n r e p r e s e n t a t i v e o f f i c e : r o o m 1 3 b 1 , t o w e r c , e l e c t r o n i c s s c i e n c e & t e c h n o l o g y b u i l d i n g s h e n n a n z h o n g r o a d s h e n z h e n , p . r . c h i n a p h o n e : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 1 f a x : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 5 |
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